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基于Cadence CHI和IVD VIP的 多核SoC系统数据一致性验证
2020年电子技术应用第8期
范君健1,晁张虎1,杨庆娜1,刘 琪1,朱 红1,单建旗2
1.天津飞腾信息技术荣鼎彩手机app下载,天津102209;2 Cadence,广东 深圳518040
摘要: 在多核的SoC系统中,不同的处理器核对内存空间和设备空间进行着大量的数据读写操作,维护Cache一致性面临严峻挑战。集中于控制流方面的验证环境搭建已非常复杂,而包含数据正确性检查的验证由于控制流程复杂、数据量大等问题而更加困难。针对这一问题,基于Cadence公司提供CHI VIP、AXI VIP和IVD VIP,实现多核环境下的系统级数据一致性验证。搭建的验证平台中采用CHI VIP通过笔者开发的CHI协议转换桥发出访存请求,使用AXI VIP收集到达主存的数据,由IVD VIP对CHI端口的请求数据与AXI端口的访存数据进行实时分析比对,实现在较高抽象层次上的激励产生和响应检查。该验证平台能够在子系统级及系统级进行数据一致性验证,具有验证环境搭建快速和功能点覆盖完备的优点。
中图分类号: TN409
文献标识码: A
DOI:10.16157/j.issn.0258-7998.209805
中文引用格式: 范君健,晁张虎,杨庆娜,等. 基于Cadence CHI和IVD VIP的多核SoC系统数据一致性验证[J].电子技术应用,2020,46(8):72-76.
英文引用格式: Fan Junjian,Chao Zhanghu,Yang Qingna,et al. Multi-core SoC based on Cadence CHI and IVD VIP system data coherence verification[J]. Application of Electronic Technique,2020,46(8):72-76.
Multi-core SoC based on Cadence CHI and IVD VIP system data coherence verification
Fan Junjian1,Chao Zhanghu1,Yang Qingna1,Liu Qi1,Zhu Hong1,Shan Jianqi2
1.Tianjin Phytium Technology Co.,Ltd.,Tianjin 102209,China;2.Cadence,Shenzhen 518040,China
Abstract: In a multi-core SoC system, different processor cores perform a large amount of data read and write operations on memory space and device space. Maintaining cache coherence is facing severe challenges. The verification environment focused on the control flow has been very complicated, and the verification including data correctness check is more difficult due to the complicated control process and large amount of data. In response to this problem, this paper is based on Cadence CHI VIP, AXI VIP and IVD VIP to achieve system-level data coherence verification in a multi-core environment. In this paper, CHI VIP is used to issue a memory access request through the CHI protocol conversion bridge developed by the author, and AXI VIP is used to collect data that arrives in the main memory, real-time analysis and comparison of the request data of the CHI port and the access data of the AXI port by the IVD VIP,to realize stimulus generation and response inspection at a higher level of abstraction. The verification platform can perform data consistency verification at the subsystem level and system level, and has the advantages of rapid verification environment construction and complete coverage of function points.
Key words : cache coherence;subsystem verification;VIP;modular verification

0 引言

    Cache(高速缓冲存储器)是存在于处理器核与主存之间的存储器,在多核的处理器系统当中,当多个Cache包含同一块数据时,如果其中任意一个Cache修改了该数据块而没有通知其他的Cache,就会产生数据不一致的情况[1]Cache一致性就是维护多个Cache数据的一致性,Cache一致性协议是多核处理器系统的核心,因此Cache一致性的验证是一项非常重要的工作。

    现阶段,Cache一致性的验证一般采用软件模拟的形式,但随着协议复杂性的增加,验证中需要覆盖的状态与路径成几何倍数增加。同时,访存数据在经过片上互联网络写入主存时要经过较长的路径,需要对流经网络的数据正确性进行检查,验证环境的复杂程度越来越高。在验证环境搭建与验证覆盖率收集方面,验证人员往往需要投入大量的精力,导致Cache一致性验证周期耗时较长。




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作者信息:

范君健1,晁张虎1,杨庆娜1,刘  琪1,朱  红1,单建旗2

(1.天津飞腾信息技术荣鼎彩手机app下载,天津102209;2 Cadence,广东 深圳518040)

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