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基于FPGA的高精度鉴相器实现
2020年电子技术应用第10期
董淑豪1,吴东岷2
1.中国科学技术大学 微电子学院,安徽 合肥230026; 2.中国科学院苏州纳米技术与纳米仿生研究所,江苏 苏州215000
摘要: 基于模拟电路的鉴相器虽然响应速度快,但是很难达到较高的精度,并且开发周期长不易优化。为了可以实时检测MEMS器件谐振时微小的相位变化,提出一种基于FPGA的高精度鉴相器。该鉴相器主要是由数字混频器、FIR数字滤波器、DDS信号发生器以及模数转换电路组成。鉴相方法是通过将被测信号与一同频、相位可调、且初始相位为90°的参考信号混频,并通过高阶FIR滤波器提取与相位有关的差频信号,调节参考信号相位使得此差频信号趋近于0,则此参考信号的相位调节量即为被测信号的相位。鉴相器的时钟频率为100 MHz,鉴相精度可以达到0.000 1°。工作频率灵活可调,并且应用于锁相环中时,可以很方便地与MEMS器件的驱动电路兼容。
关键词: FPGA FIR 鉴相器 DDS MEMS
中图分类号: TN763.3
文献标识码: A
DOI:10.16157/j.issn.0258-7998.200377
中文引用格式: 董淑豪,吴东岷. 基于FPGA的高精度鉴相器实现[J].电子技术应用,2020,46(10):57-60,78.
英文引用格式: Dong Shuhao,Wu Dongmin. Realization of high precision phase detector based on FPGA[J]. Application of Electronic Technique,2020,46(10):57-60,78.
Realization of high precision phase detector based on FPGA
Dong Shuhao1,Wu Dongmin2
1.School of Microelectronics,University of Science and Technology of China,Hefei 230026,China; 2.Suzhou Institue of Nano-Tech and Nano-Bionics,Suzhou 215000,China
Abstract: Although the response speed of the phase detector based on analog circuit is fast, it is difficult to achieve high precision, and the development cycle is long and difficult to optimize. In order to detect the tiny phase change of micro-electro-mechanical system(MEMS) devices in real time, a high-precision phase detector based on field programmable gate array(FPGA) is proposed. The phase detector is mainly composed of digital mixer, finite impulse response(FIR) digital filter, direct digital synthesis(DDS) signal generator and analog digital converter conversion circuit. The phase detection method is to mix the measured signal with the reference signal with the same frequency, adjustable phase and initial phase of 90°, and extract the phase related difference frequency signal through high-order FIR filter, adjust the reference signal phase to make the difference frequency signal close to 0, then the phase adjustment amount of the reference signal is the phase of the measured signal. The clock frequency of the phase detector is 100 MHz, and the phase accuracy can reach 0.000 1°. The working frequency is flexible and adjustable. When it is used in PLL, it can be easily compatible with the driving circuit of MEMS devices.
Key words : FPGA;FIR;phase detector;DDS;MEMS

0 引言

    微机电系统(Micro-Electro-Mechanical System,MEMS),体积小、功耗低、谐振频率高、光学特性好[1],在医疗、军事、科研等领域得到广泛应用。在MEMS微振镜的同步控制过程中,传统的模拟鉴相器很难达到较高精度,并且模拟鉴相器开发周期长,不易优化。基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的数字鉴相器可以大大提高鉴相精度[2],并且灵活可调,方便实现MEMS微镜的同步控制。




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作者信息:

董淑豪1,吴东岷2

(1。中国科学技术大学 微电子学院,安徽 合肥230026;

2.中国科学院苏州纳米技术与纳米仿生研究所,江苏 苏州215000)

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